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CPU cache
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#	Item
341	Locating Cache Performance Bottlenecks Using Data Profiling Aleksey Pesterev Nickolai Zeldovich Robert T. Morris Add to Reading List Source URL: pdos.csail.mit.edu Language: English - Date: 2015-04-29 10:31:15 Computer memory Computing CPU cache Data Memcached Cache Computer hardware Central processing unit
342	Cross-VM Side Channels and Their Use to Extract Private Keys Yinqian Zhang Ari Juels Add to Reading List Source URL: pages.cs.wisc.edu Language: English - Date: 2012-12-24 14:28:56 Key management Electronic commerce RSA Side channel attack Public key fingerprint Xen Ciphertext CPU cache Key Cryptography Public-key cryptography Cache
343	Hitachi SuperH RISC engine SH7750 Series SH7750, SH7750S Hardware Manual Add to Reading List Source URL: www.boob.co.uk Language: English - Date: 2001-05-18 07:14:44 Computing Microcontrollers Virtual memory Instruction set architectures Central processing unit Memory management unit CPU cache Dynamic random-access memory SuperH Computer hardware Computer architecture Computer memory
344	Lecture 00: Notes to Lecturers of CS 252 Professor David A. Patterson Computer Science 252 Spring 1998 Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 1998-05-12 10:02:01 Cache CPU cache
345	Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines Brian R. Gaeke1, Parry Husbands2, Xiaoye S. Li2, Leonid Oliker2, Katherine A. Yelick1,2, and Rupak Biswas3 1 Computer Science Division, University of California Add to Reading List Source URL: iram.cs.berkeley.edu Language: English - Date: 2003-01-09 09:13:00 Parallel computing Central processing unit Computer memory Classes of computers CPU cache Benchmark Vector processor Memory bandwidth Cell Computing Computer hardware Computer architecture
346	SuperH™ (SH) 32-Bit RISC MCU/MPU Series SH7750 High-Performance RISC Engine Programming Manual Add to Reading List Source URL: www.boob.co.uk Language: English - Date: 2001-02-14 21:50:32 Central processing unit Instruction set architectures Virtual memory Computer memory Memory management unit SuperH CPU cache Reduced instruction set computing Addressing mode Computer architecture Computer hardware Computing
347	Appears in the Proceedings of the 21st International Symposium on High Performance Computer Architecture (HPCA), 2015 Scaling Distributed Cache Hierarchies through Computation and Data Co-Scheduling Nathan Beckmann, Po- Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2015-01-08 12:13:44 Central processing unit Computer architecture Microprocessors CPU cache Cache Microarchitecture Parallel computing Dynamic random-access memory CAS latency Computer hardware Computer memory Computing
348	RadixVM: Scalable address spaces for multithreaded applications Austin T. Clements, M. Frans Kaashoek, and Nickolai Zeldovich MIT CSAIL A BSTRACT Add to Reading List Source URL: pdos.csail.mit.edu Language: English - Date: 2015-04-29 10:31:16 Virtual memory Central processing unit CPU cache Mmap Page table Translation lookaside buffer C dynamic memory allocation Radix tree Page Memory management Computing Computer memory
349	CHAPTER EIGHT Writing Centers and WAC JOAN A. Add to Reading List Source URL: wac.colostate.edu Language: English - Date: 2011-03-11 16:52:44 Cache Central processing unit Computer memory Sandy Bridge L3 Computing Computer hardware Computer architecture CPU cache
350	Intel® OpenSource HD Graphics Programmer’s Reference Manual (PRM) Volume 1 Part 7: L3$/URB (Ivy Bridge) For the 2012 Intel® Core™ Processor Family Add to Reading List Source URL: files.renderingpipeline.com Language: English - Date: 2013-09-24 10:27:25 Cache Central processing unit Computer memory Sandy Bridge L3 Computing Computer hardware Computer architecture CPU cache

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